1. Field of Invention
The invention relates to a technique for determining key transistor model quantities including device mobility for semiconductor devices and, more particularly to a technique for determining how these quantities are affected by the layout of a semiconductor device that uses nitride liner films to apply stress in a transistor device channel.
2. Description of Related Art
Stress can be applied in semiconductor devices to increase the mobility of electrons or holes in such devices. For example, stress can be applied to the channel of field effect transistors (FETs) by using intrinsically stressed films such as the liner film that is used normally in the formation of metal contact (MC) terminals to the source and drain regions of the FET. Stress films can typically be nitride films because nitride films are compatible with the silicon fabrication process steps used for contact formation and etching. Liner films exert stress on an isolated FET gate (also called the “victim” gate) by adhering to adjacent surfaces such as the wafer surface and “pushing” or “pulling” on the gate structures. The stress is transferred primarily through the gate spacers, which are self-aligned to the gate polysilicon (PC). A liner-film with inherent tensile stress transfers tensile stress, and is used for improving electron mobility in n-type FETs (NFETS), while a liner film with inherent compressive stress transfers compressive stress, and is used for improving hole mobility in p-type FETs (PFETs). One factor that dilutes the effectiveness of nitride liners is that the contact metallurgy, particularly to the source and drain regions, requires parts of the liner to be etched away very near the device. This not only disrupts the ability of the long film runway to transfer stress, but also moves the singularity/edge that would influence the channel further away, severely reducing the stress benefit. Other structures that are on the same physical level above the silicon surface such as contact metallurgy and that interrupt the film can also have the same effect. An example of such a structure is polysilicon wiring. Further, an even more serious concern is that these structures can be arbitrarily designed and therefore have a difficult to predict effect on performance, either positive or negative. Layout-dependent factors that influence the stress include the spacing between the victim gate and adjacent structures, the dimensions of these adjacent structures, the amount of contact coverage (or source/drain strapping), and in the case of dual-stress liner technologies (one liner for NFETS and a different liner for PFETS), the proximity of the interface between the two liner films. Small changes in FET layout can introduce noticeable shifts in drive current, and this variation can appear to change device to device across a chip. Not accounting for this magnitude of variation in stress benefit can seriously underpredict or overpredict electrical performance in circuit simulation. Furthermore, with information about the influence of stress on a given layout, circuit designers can optimize their designs for exploiting stress.
Previously developed layout-sensitive effects that have been studied include shallow trench isolation (STI) stress effects and N-Well scattering effects. The STI stress effect is accounted for by obtaining the length and width of the active area (silicon island surrounded by STI) of the semiconductor device and adjusting the mobility as a function of these two parameters. The primary cause of stress in the STI process is that a compressive stress is typically applied in both longitudinal (orthogonal to the gate) and transverse (parallel to the gate) directions, altering the silicon band structure locally. Such a stress degrades the NFETs while benefiting the PFET. The stress-based adjustment is then based purely on empirical data from a set of specifically designed macros that span the complete length/width active area parameter space. Then for any given active area length/width, one can interpolate the results. Moreover, parametric fits to the mobility impact can be experimentally obtained from experimental data.
The N-well scattering effect occurs when implant shadowing of dopant ions scatters to unintended locations from relatively thick resist layers. N-well implant scattering is therefore also layout sensitive, but this sensitivity is unrelated to stress effects. That is, the influence of N-well implant scattering alters the voltage threshold (Vt) of devices that happen to be close by.
This impact causes circuit operability problems and therefore must be properly accounted for. The modeling methodology is to identify the N-well resist proximity based on plan view layout and defining, again through empirical calibration, and based on distances from this N-well resist, the threshold voltage impact of the N-well scattering. One technique for modeling a structure influenced by N-well implant scattering is described in commonly-owned, co-pending U.S. patent application Ser. No. 10/248,853 (Pub. No. US2004/0034517A1).
It would be highly desirable to provide a system and method that extends the above concepts to accurately account for layout-induced changes in nitride liner stress in semiconductor devices.